PCIe Gen4 / CCIX top-block — 2 GHz timing closure

PCIe Gen4 / CCIX top-block — 2 GHz timing closure

PCIe Gen4 / CCIX top-block — 2 GHz timing closure

CCIX cache-coherent interconnect for AI training accelerators. Multi-source CTS across 388+412 clock domains, AOCV STA sign-off on CCIX link, 4 SerDes PMA custom routes with NDR, and full DRC/DFM sign-off.

Back to Partners Discuss a similar project

Related Posts

View all partners
Hierarchical APR on TSMC N3E — AXMM top-block
Partners

Hierarchical APR on TSMC N3E — AXMM top-block

4-partition hierarchical PnR for an edge AI inference processor. IOPin budgeting, cross-partition routing congestion resolution, ELVT leakage containment, EUV multi-patterning DRC/DFM compliance, and MCMM STA sign-off on schedule.
RTL-to-GDSII full-chip — 150M instances
Partners

RTL-to-GDSII full-chip — 150M instances

Turnkey hierarchical PnR for an AI inference SoC across 26 partitions, 8 hardened IPs, 596 clock domains. MCMM/POCV STA sign-off, EM-IR closure, custom PG mesh routing, full-chip DRC/LVS/ERC/ANT sign-off.
Largest-die RTL-to-GDSII — 17.5 x 28 mm
Partners

Largest-die RTL-to-GDSII — 17.5 x 28 mm

Turnkey full-chip PnR for an Automotive ADAS vision SoC. 13 partitions, 396 clock domains, 10LM5X2Y2ZUTRDL stack. AOCV MCMM STA sign-off, EM-IR closure, full DRC/LVS/ERC/ANT/ICOVL/TCD sign-off.

NEED SPECIALIZED SEMICONDUCTOR DESIGN SUPPORT?

Talk to our experts