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TECHNOLOGY

Chiplet Disaggregation
CHIPLET
DISAGGREGATION
Interconnect Standards
INTERCONNECT
STANDARDS
AI-Centric SOC Building
AI-CENTRIC SOC
BUILDING

DESIGN SERVICE

Specification to GDSII +
End-to-end turnkey silicon delivery. We transform high-level system architectural requirements into silicon-proven GDSII/OASIS files ready for foundry tapeout.
RTL to GDSII +
Full physical implementation flow: logic synthesis, DFT insertion, hierarchical floorplanning, clock tree synthesis (CTS), routing, and multi-corner STA timing closure.
Netlist to GDSII +
Expert APR execution from gate-level netlists with rigorous physical verification (DRC, LVS, ERC, Antenna), IR-drop power integrity signoff, and DFM optimization.

IP SERVICE

IP Development +
Custom silicon IP block design for high-speed SerDes, memory interfaces, standard cell libraries, and AI acceleration processing units.
Circuit Design +
Analog, mixed-signal, and RF circuit design, power management ICs (PMIC), PLLs, high-precision ADCs/DACs across leading foundry PDKs.
Custom Layout +
Full-custom layout optimization for FinFET and planar nodes with strict matching, thermal symmetry, low parasitic extraction, and ESD/latch-up robustness.

VNCHIP R&D

Partners Projects
VNCHIP R&D Engineering Team
Cleanroom Workstations
VNCHIP Institute Team

LQ INNOVATIONS and VNCHIP Joint Stock Company Announce Strategic Research Collaboration to Develop a New Intellectual Property Block

Ho Chi Minh City, October 2025 - LQ INNOVATIONS, led by Mr. Le Trong Quang, and VNCHIP Joint Stock Company proudly announce the launch of the first official research project under the VNCHIP Institute, marking a pivotal milestone in Vietnam’s semiconductor research and development landscape.

This collaboration marks a significant step toward advancing domestic chip design capabilities through the integration of cutting-edge research, empathic leadership, and top-tier engineering talent from both organizations. The project underscores the shared vision of LQ INNOVATIONS and VNCHIP to foster innovation, enhance professional capacity, and contribute to the sustainable growth of Vietnam’s semiconductor industry.

Spanning one year, the project will involve a dedicated team of 2–3 senior engineers and 6–8 fresh graduates, combining hands-on research with an intensive training program for VNCHIP talents. The initiative’s primary goals are to deliver a production-ready IP cluster and to build a skilled engineering team capable of driving VNCHIP’s next-generation System-on-Chip (SoC) and chiplet developments.

As the first research initiative of VNCHIP Institute, this collaboration not only lays the foundation for future R&D excellence but also demonstrates VNCHIP’s commitment to cultivating Vietnam’s semiconductor talent ecosystem and accelerating the nation’s technological self-reliance.

SUCCESS IN ACTION

Excellence in semiconductor design delivery through proven methodologies and technical innovation.

Hierarchical APR on TSMC N3E

Hierarchical APR on TSMC N3E — AXMM top-block

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Hierarchical APR on TSMC N3E

Hierarchical APR on TSMC N3E — AXMM top-block

Lorem ipsum dolor sit amet, consectetuer adipiscing elit, sed diam nonummy nibh euismod tincidunt ut laoreet dolore magna aliquam erat volutpat. Ut wisi enim ad

Hierarchical APR on TSMC N3E

Hierarchical APR on TSMC N3E — AXMM top-block

Lorem ipsum dolor sit amet, consectetuer adipiscing elit, sed diam nonummy nibh euismod tincidunt ut laoreet dolore magna aliquam erat volutpat. Ut wisi enim ad

PARTNER VALUES

“EMPOWERING OUR PARTNERS WITH EXPERT DESIGN SOLUTIONS WHILE LEVERAGING COLLABORATION TO ACHIEVE GLOBAL STANDARDS.”

UNIVERSITY PARTNERS

HCMUTE University Partner
UIT University Partner
Vietnamese-German University Partner
Bach Khoa Ho Chi Minh City Partner
National Innovation Center NIC

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