CXL.io / .cache / .mem interconnect block
CXL protocol stack enabling AI server memory coherency and pooling. 1,536 clock domains, IP-boundary STA sign-off, EM-IR closure, post-layout parasitic extraction for STA. Full DRC/LVS sign-off.
CXL protocol stack enabling AI server memory coherency and pooling. 1,536 clock domains, IP-boundary STA sign-off, EM-IR closure, post-layout parasitic extraction for STA. Full DRC/LVS sign-off.
4-partition hierarchical PnR for an edge AI inference processor. IOPin budgeting, cross-partition routing congestion resolution, ELVT leakage containment, EUV multi-patterning DRC/DFM compliance, and MCMM STA sign-off on schedule.
Turnkey hierarchical PnR for an AI inference SoC across 26 partitions, 8 hardened IPs, 596 clock domains. MCMM/POCV STA sign-off, EM-IR closure, custom PG mesh routing, full-chip DRC/LVS/ERC/ANT sign-off.
Turnkey full-chip PnR for an Automotive ADAS vision SoC. 13 partitions, 396 clock domains, 10LM5X2Y2ZUTRDL stack. AOCV MCMM STA sign-off, EM-IR closure, full DRC/LVS/ERC/ANT/ICOVL/TCD sign-off.